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| ltc2415/ltc2415-1 1 sn2415 24151fs n 2 speed up version of the ltc2410/ltc2413: 15hz output rate, 50hz or 60hz notchltc2415; 13.75hz output rate, simultaneous 50hz/60hz notchltc2415-1 n differential input and differential reference with gnd to v cc common mode range n 2ppm inl, no missing codes n 2.5ppm gain error n 0.23ppm noise n single conversion settling time for multiplexed applications n internal oscillatorno external components required n 24-bit adc in narrow ssop-16 package (so-8 footprint) n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown the ltc ? 2415/2415-1 are micropower 24-bit differential ds analog to digital converters with integrated oscillator, 2ppm inl, 0.23ppm rms noise and a 2.7v to 5.5v supply range. they use delta-sigma technology and provide single cycle settling time for multiplexed applications. through a single pin, the ltc2415 can be configured for better than 110db input differential mode rejection at 50hz or 60hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. the ltc2415-1 can be configured for better than 87db input differential mode rejection over the range of 49hz to 61.2hz (50hz and 60hz 2% simultaneously). the inter- nal oscillator requires no external frequency setting com- ponents. the converters accept any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement configurations. the full- scale differential input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set anywhere within the gnd to v cc range of the ltc2415/ltc2415-1. the dc common mode input rejec- tion is better than 140db. the ltc2415/ltc2415-1 communicate through a flexible 3-wire digital interface which is compatible with spi and microwire tm protocols. , ltc and lt are registered trademarks of linear technology corporation. 24-bit no latency ds tm adcs with differential input and differential reference no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref = internal osc/50hz rejection (ltc2415) = external clock source = internal osc/60hz rejection (ltc2415) = internal 50hz/60hz rejection (ltc2415-1) 3-wire spi interface 1 f 2.7v to 5.5v ltc2415/ ltc2415-1 2415 ta01 v cc ltc2415/ ltc2415-1 in + ref + v cc ref v cc gnd f o in 1 f sdo 3-wire spi interface sck 2415 ta02 cs 12 3 2 1, 7, 8 9, 10, 15, 16 14 5 6 4 13 11 bridge impedance 100 to 10k features descriptio u typical applicatio s u applicatio s u n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain gage transducers n instrumentation n data acquisition n industrial process control n 6-digit dvms
ltc2415/ltc2415-1 2 sn2415 24151fs absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics (notes 1, 2) order part number supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2415c/ltc2415-1c ........................... 0 c to 70 c ltc2415i/ltc2415-1i ........................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 95 c/w ltc2415cgn ltc2415ign ltc2415-1cgn ltc2415-1ign parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 24 bits integral nonlinearity 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 1 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) l 2 14 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 5 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, l 0.5 2 mv gnd in + = in C v cc , (note 14) offset error drift 2.5v ref + v cc , ref C = gnd, 20 nv/ c gnd in + = in C v cc positive gain error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.75ref + , in C = 0.25 ? ref + positive gain error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative gain error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.25 ? ref + , in C = 0.75 ? ref + negative gain error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + output noise 5v v cc 5.5v, ref + = 5v, ref C = gnd, 1.1 m v rms gnd in C = in + v cc , (note 13) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) gn part marking 2415 2415i 24151 24151i top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc ref + ref in + in gnd gnd gnd gnd f o sck sdo cs gnd gnd consult ltc marketing for parts specified with wider operating temperature ranges. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co verter characteristics u parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + v cc ltc2415/ltc2415-1 3 sn2415 24151fs symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage l gnd C 0.3v v cc + 0.3v v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1v v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 18 pf c s (in C )in C sampling capacitance 18 pf c s (ref + )ref + sampling capacitance 18 pf c s (ref C )ref C sampling capacitance 18 pf i dc_leak (in + )in + dc leakage current cs = v cc , in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current cs = v cc , in C = gnd l C10 1 10 na i dc_leak (ref + )ref + dc leakage current cs = v cc , ref + = 5v l C10 1 10 na i dc_leak (ref C )ref C dc leakage current cs = v cc , ref C = gnd l C10 1 10 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) parameter conditions min typ max units co verter characteristics u a alog i put a u d refere ce uu u input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 60hz 2% (ltc2415) gnd in C = in + v cc , (note 7) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 50hz 2% (ltc2415) gnd in C = in + v cc , (note 8) input normal mode rejection (note 7) l 110 140 db 60hz 2% (ltc2415) input normal mode rejection (note 8) l 110 140 db 50hz 2% (ltc2415) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 49hz to 61.2hz (ltc2415-1) gnd in C = in + v cc , (note 7) input normal mode rejection f o = gnd l 87 db 49hz to 61.2hz (ltc2415-1) input normal mode rejection external oscillator l 87 db external clock f eosc /2560 14% (ltc2415-1) input normal mode rejection external oscillator l 110 140 db external clock f eosc /2560 4% (ltc2415-1) reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd power supply rejection, dc ref + = v cc , ref C = gnd, in C = in + = gnd 100 db power supply rejection, 60hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 7) 120 db power supply rejection, 50hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 8) 120 db ltc2415/ltc2415-1 4 sn2415 24151fs symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 20 30 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C800 m a l v cc C 0.5 v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C800 m a (note 10) l v cc C 0.5 v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs uu power require e ts w u ltc2415/ltc2415-1 5 sn2415 24151fs note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: refer to offset accuracy and drift in the applications information section. symbol parameter conditions min typ max units f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time (ltc2415) f o = 0v l 65.43 66.77 68.1 ms f o = v cc l 78.52 80.12 81.72 ms external oscillator (note 11) l 10278/f eosc (in khz) ms conversion time (ltc2415-1) f o = 0v l 71.3 72.8 74.3 ms external oscillator (note 11) l 10278/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10), ltc2415 19.2 khz internal oscillator (note 10), ltc2415-1 17.5 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 12), ltc2415 l 1.64 1.67 1.70 ms internal oscillator (notes 10, 12), ltc2415-1 l 1.80 1.83 1.86 ms external oscillator (notes 10, 11) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 9) l 32/f esck (in khz) ms t 1 cs to sdo low z l 0 200 ns t2 cs - to sdo high z l 0 200 ns t3 cs to sck (note 10) l 0 200 ns t4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics w u ltc2415/ltc2415-1 6 sn2415 24151fs v in (v) 2.5 2 1.5 ? 0.5 0 0.5 1 1.5 2 2.5 tue (ppm of v ref ) 2415 g01 106.5 106.0 105.5 105.0 104.5 104.0 103.5 v cc = 5v v ref = 5v v incm = 2.5v ref + = 5v ref = gnd f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) 1.25 0.75 0.25 0.25 0.75 1.25 tue (ppm of v ref ) 2415 g02 215 213 211 209 207 205 v cc = 5v v ref = 2.5v v incm = 1.25v ref + = 2.5v ref = gnd f o = gnd t a = 90 c t a = 45 c t a = 25 c v in (v) 1.25 0.75 0.25 0.25 0.75 1.25 tue (ppm of v ref ) 2415 g03 125 121 117 113 109 105 v cc = 2.7v v ref = 2.5v v incm = 1.25v ref + = 2.5v ref = gnd f o = gnd t a = 45 c t a = 25 c t a = 90 c v in (v) 2.5 2 1.5 ? 0.5 0 0.5 1 1.5 2 2.5 inl error (ppm of v ref ) 2415 g04 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 v cc = 5v v ref = 5v v incm = 2.5v ref + = 5v ref = gnd f o = gnd t a = 25 c t a = 45 c t a = 90 c v in (v) 1.25 0.75 0.25 0.25 0.75 1.25 inl error (ppm of v ref ) 2415 g05 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 v cc = 5v v ref = 2.5v v incm = 1.25v ref + = 2.5v ref = gnd f o = gnd t a = 45 c t a = 25 c t a = 90 c v in (v) 1.25 0.75 0.25 0.25 0.75 1.25 inl error (ppm of v ref ) 2415 g05 10 8 6 4 2 0 ? ? ? ? ?0 v cc = 2.7v v ref = 2.5v v incm = 1.25v ref + = 2.5v ref = gnd f o = gnd t a = 90 c t a = 45 c t a = 25 c output code (ppm of v ref ) 105.5 ?04.8 ?04 ?03.3 ?02.5 number of readings (%) 2415 g07 12 10 8 6 4 2 0 gaussian distribution m = ?03.5ppm s = 0.27ppm 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c output code (ppm of v ref ) 105 ?04.5 ?04 ?03.5 ?03 number of readings (%) 2415 g08 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 460800hz t a = 25 c gaussian distribution m = ?04.0ppm s = 0.25ppm output code (ppm of v ref ) ?02 ?99.5 ?97 ?94.5 ?92 number of readings (%) 2415 g09 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 1075200hz t a = 25 c gaussian distribution m = ?99.0ppm s = 0.9ppm total unadjusted error over temperature (v cc = 5v, v ref = 5v) total unadjusted error over temperature (v cc = 5v, v ref = 2.5v) total unadjusted error over temperature (v cc = 2.7v, v ref = 2.5v) integral nonlinearity over temperature (v cc = 5v, v ref = 5v) integral nonlinearity over temperature (v cc = 5v, v ref = 2.5v) integral nonlinearity over temperature (v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 15hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 45hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 105hz, v cc = 5v, v ref = 5v) typical perfor a ce characteristics uw ltc2415/ltc2415-1 7 sn2415 24151fs output code (ppm of v ref ) ?12 ?10.5 ?09 ?07.5 ?06 number of readings (%) 2415 g10 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = ?09.2ppm s = 0.56ppm output code (ppm of v ref ) ?11.5 ?10.5 ?09.5 ?08.5 ?07.5 number of readings (%) 2415 g11 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = ?09.3ppm s = 0.49ppm output code (ppm of v ref ) ?10 ?07 ?04 ?01 ?98 number of readings (%) 2415 g12 15 12 9 6 3 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = ?06.5ppm s = 1.07ppm output code (ppm of v ref ) 116 ?14.5 ?13 ?11.5 ?10 number of readings (%) 2415 g13 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = ?13.1ppm s = 0.59ppm output code (ppm of v ref ) 112 ?10.9 ?09.8 ?08.6 ?07.5 number of readings (%) 2415 g14 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = ?09.8ppm s = 0.50ppm output code (ppm of v ref ) ?0 ?5.5 ?1 ?6.5 ?2 number of readings (%) 2415 g15 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = ?0.5ppm s = 1.90ppm output code (ppm of v ref ) 103 ?03.5 ?04 ?04.5 ?05 number of readings (%) 2415 g16 12 10 8 6 4 2 0 v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c gaussian distribution m = ?03.9ppm s = 0.27ppm time (hrs) 05 10 15 20 25 30 35 40 45 50 55 60 adc readings (ppm of v ref ) 2415 g17 ?01.0 ?01.5 ?02.0 ?02.5 ?03.0 ?03.5 ?04.0 ?04.5 ?05.0 ?05.5 v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c input differential voltage (v) 2.5 2 1.5 ? 0.5 0 0.5 1 1.5 2 2.5 rms noise (ppm of v ref ) 2415 g18 0.5 0.4 0.3 0.2 0.1 0 v cc = 5v v ref = 5v v incm = 2.5v ref + = 5v ref = gnd f o = gnd t a = 25 c noise histogram (output rate = 15hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 45hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 105hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 15hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 45hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 105hz, v cc = 2.7v, v ref = 2.5v) long-term histogram (60hrs) consecutive adc readings vs time rms noise vs input differential voltage typical perfor a ce characteristics uw ltc2415/ltc2415-1 8 sn2415 24151fs temperature ( c) 50 25 0 25 50 75 100 rms noise (nv) 2415 g20 1400 1250 1100 950 800 v cc = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rms noise (nv) 2415 g21 1560 1520 1480 1440 1400 1360 1320 1280 v ref = 2.5v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c v ref (v) 0 1 2 3 4 0.5 1.5 2.5 3.5 4.5 5 rms noise (nv) 2415 g22 1600 1400 1200 1000 800 v cc = 5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c v incm (v) 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 offset error (ppm of v ref ) 2415 g23 103.0 103.4 103.8 104.2 104.6 105.0 v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = v incm in = v incm f o = gnd t a = 25 c temperature ( c) 50 25 0 25 50 75 100 offset error (ppm of v ref ) 2415 g24 103.8 104.0 104.2 104.4 104.6 v cc = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 offset error (ppm of v ref ) 2415 g25 110 130 150 170 190 210 230 v ref = 2.5v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c v cc and v ref (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 offset error (ppm of v ref ) 2415 g26 103.2 103.6 104.0 104.4 104.8 105.2 ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c temperature ( c) ?5 ?0 ?5 0 15 30 45 60 75 90 + full-scale error (ppm of v ref ) 2415 g27 3 2 1 0 ? ? ? v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = gnd f o = gnd typical perfor a ce characteristics uw v incm (v) 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 rms noise (nv) 2415 g19 1800 1600 1400 1200 1000 in + = v incm in = v incm f o = gnd t a = 25 c v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd rms noise vs v incm rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v incm offset error vs temperature (t a ) offset error vs v cc offset error vs v cc and v ref + full-scale error vs temperature (t a ) ltc2415/ltc2415-1 9 sn2415 24151fs typical perfor a ce characteristics uw v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 + full-scale error (ppm of v ref ) 2415 g28 5 4 3 2 1 0 v ref = 2.5v ref + = 2.5v ref = gnd in + = 1.25v in = gnd f o = gnd t a = 25 c v ref (v) 1 2 3 4 0.5 1.5 2.5 3.5 4.5 5 + full-scale error (ppm of v ref ) 2415 g29 8 4 0 ? ? v cc = 5v ref + = v ref ref = gnd in + = 0.5 ?ref + in = gnd f o = gnd t a = 25 c temperature ( c) ?5 ?0 ?5 0 15 30 45 60 75 90 full-scale error (ppm of v ref ) 2415 g30 0 ? ? ? ? ? ? v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 full-scale error (ppm of v ref ) 2415 g31 0 ? ? ? ? ? v ref = 2.5v ref + = 2.5v ref = gnd in + = gnd in = 1.25v f o = gnd t a = 25 c v ref (v) 1 2 3 4 0.5 1.5 2.5 3.5 4.5 5 full-scale error (ppm of v ref ) 2415 g32 8 4 0 ? ? ?2 v cc = 5v ref + = v ref ref = gnd in + = gnd in = 0.5 ?ref + f o = gnd t a = 25 c frequency at v cc (hz) 050 100 150 200 250 rejection (db) 2415 g33 0 ?0 ?0 ?0 ?0 100 120 v cc = 4.1v dc + 1.4v ac ref + = 2.5v ref = gnd in + = in = gnd f o = gnd t a = 25 c frequency at v cc (hz) 1 100 10000 1000000 rejection (db) 2415 g34 0 ?0 ?0 ?0 ?0 100 120 ref + = 2.5v ref = gnd in + = in = gnd f o = gnd t a = 25 c frequency at v cc (hz) 15200 15300 15400 15500 rejection (db) 2415 g35 0 ?0 ?0 ?0 ?0 100 120 v cc = 4.1v dc + 0.7v ac ref + = 2.5v ref = gnd in + = in = gnd f o = gnd t a = 25 c +full-scale error vs v cc +full-scale error vs v ref C full-scale error vs temperature (t a ) C full-scale error vs v cc C full-scale error vs v ref psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc temperature ( c) ?5 ?0 ?5 0 15 30 45 60 75 90 supply current ( a) 2415 g36 220 210 200 190 180 170 160 150 140 v ref + = v cc v ref = gnd v in + = v in = gnd f o = gnd cs = gnd sck = sdo = n/c v cc = 5.5v v cc = 4.1v v cc = 2.7v conversion current vs temperature (t a ) ltc2415/ltc2415-1 10 sn2415 24151fs gnd (pins 1, 7, 8, 9, 10, 15, 16): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd (pin 1) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C 0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range the converter produces unique overrange and underrange output codes. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull- up is automatically activated in internal serial clock op- eration mode. the serial clock operation mode is deter- mined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. pi fu ctio s uuu typical perfor a ce characteristics uw output data rate (readings/sec) 010 20 30 40 50 60 70 80 90 100 supply current ( a) 2415 g37 1000 900 800 700 600 500 400 300 200 100 0 v cc = 5v ref + = 5v ref = gnd in + = gnd in = gnd f o = ext osc cs = gnd sck =n/c sdo = n/c temperature ( c) ?5 ?0 ?5 0 15 30 45 60 75 90 supply current ( a) 2415 g38 25 24 23 22 21 20 19 18 17 16 15 v ref + = v cc v ref = gnd v in + = v in = gnd f o = gnd cs = v cc sck = sdo = n/c v cc = 5.5v v cc = 4.1v v cc = 2.7v conversion current vs output data rate sleep current vs temperature (t a ) ltc2415/ltc2415-1 11 sn2415 24151fs fu ctio al block diagra uu w figure 1. functional block diagram autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in sdo sck ref + ref cs f o (int/ext) 2415 fd ? + f o (pin 14): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (ltc2415 only), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz (ltc2415) or simultaneous 50hz/60hz (ltc2415-1). when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter first null is located at a frequency f eosc /2560. pi fu ctio s uuu test circuits 1.69k sdo 2415 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2415 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc ltc2415/ltc2415-1 12 sn2415 24151fs applicatio s i for atio wu u u figure 2. ltc2415 state transition diagram converter operation converter operation cycle the ltc2415/ltc2415-1 are low power, delta-sigma ana- log-to-digital converters with an easy to use 3-wire serial interface (see figure 1). their operation is made up of three states. the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select (cs). is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2415/ltc2415-1 offer several flexible modes of op- eration (internal or external sck and free-running conver- sion modes). these various modes do not require pro- gramming configuration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2415/ltc2415-1 incorporate a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2415 achieves a minimum of 110db rejection at the line frequency (50hz or 60hz 2%), while the ltc2415-1 achieves a minimum of 87db rejection at 50hz 2% and 60hz 2% simultaneously. ease of use the ltc2415/ltc2415-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. convert sleep data output 2415 f02 true false cs = low and sck initially, the ltc2415/ltc2415-1 perform a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by an order of magnitude if cs is high. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data ltc2415/ltc2415-1 13 sn2415 24151fs applicatio s i for atio wu u u the ltc2415/ltc2415-1 perform a full-scale calibration every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. the advantage of continuous calibration is extreme stability of full-scale readings with respect to time, supply voltage change and temperature drift. unlike the ltc2410 and ltc2413, the ltc2415 and ltc2415-1 do not perform an offset calibration every conversion cycle. this enables the ltc2415/ltc2415-1 to double their output rate while maintaining line frequency rejection. the initial offset of the ltc2415/ltc2415-1 is within 2mv independent of v ref . based on the ltc2415/ ltc2415-1 new modulator architecture, the temperature drift of the offset is less then 0.01ppm/ c. more informa- tion on the ltc2415/ltc2415-1 offset is described in the offset accuracy and drift section of this data sheet. power-up sequence the ltc2415/ltc2415-1 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2415/ltc2415-1 start a normal conversion cycle and follow the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range these converters accept a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2415/ltc2415-1 can accept a differential refer- ence voltage from 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end cir- cuits, and as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolu- tion. on the other hand, a reduced reference voltage will improve the converters overall inl performance. a re- duced reference voltage will also improve the converter performance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). input voltage range the analog input is truly differential with an absolute/ common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2415/ltc2415-1 con- vert the bipolar differential input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converters indicate the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the perfor- mance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. the effect of the series resistance on the converter accuracy can be evalu- ated from the curves presented in the input current/ reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. ltc2415/ltc2415-1 14 sn2415 24151fs applicatio s i for atio wu u u output data format the ltc2415/ltc2415-1 serial output data stream is 32 bits long. the first 3 bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2415/ltc2415-1 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb first. bit 5 is the least significant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. offset accuracy and drift unlike the ltc2410/ltc2413 and the entire ltc2400 fam- ily, the ltc2415/ltc2415-1 do not perform an offset calibration every cycle. the reason for this is to increase the data output rate while maintaining line frequency rejection. while the initial accuracy of the ltc2415/ltc2415-1 offset is within 2mv (see figure 4) several unique proper- ties of the ltc2415/ltc2415-1 architecture nearly elimi- nate the drift of the offset error with respect to temperature and supply. as shown in figure 5, the offset variation with temperature is less than 0.6ppm over the complete temperature range of C50 c to 100 c. this corresponds to a temperature drift of 0.004ppm/ c. ltc2415/ltc2415-1 15 sn2415 24151fs table 2. ltc2415/ltc2415-1 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 0 v in * eoc dmy sig msb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 3. output data timing applicatio s i for atio wu u u msb sig ? 12345 262732 bit 0 bit 27 bit 5 lsb 24 bit 28 bit 29 bit 30 sdo sck cs eoc bit 31 sleep data output conversion 2415 f03 hi-z v cc (v) 2.5 offset (ppm) 50 0 ?0 ?00 ?50 ?00 ?50 3.0 3.5 4.0 4.5 2415 f04 5.0 5.5 v ref = 2.5v t a = 25 c part no.1 part no.2 part no.3 temperature ( c) ?0 offset error (ppm of v ref ) ?03.8 ?04.0 ?04.2 ?04.4 ?04.6 ?5 0 25 50 2415 f05 75 100 v cc and v ref (v) 2.7 offset error (ppm of v ref ) ?03.0 ?03.5 ?04.0 ?04.5 ?05.0 ?05.5 3.5 4.3 4.7 2415 f06 3.1 3.9 5.1 5.5 v cc = 5v v ref = 5v ref + = 5v ref = gnd v in = 0v in + = gnd in = gnd f o = gnd t a =100 c t a = 50 c t a =25 c figure 4. offset vs v cc figure 5. offset vs temperature figure 6. offset vs v cc (v ref = v cc ) while the variation in offset with supply voltage is propor- tional to v cc (see figure 4), several characteristics of this variation can be used to eliminate the effects. first, the variation with respect to supply voltage is linear. second, the magnitude of the offset error decreases with de- creased supply voltage. third, the offset error increases with increased reference voltage with an equal and oppo- site magnitude to the supply voltage variation. as a result, by tying v cc to v ref , the variation with supply can be nearly eliminated, see figure 6. the variation with supply is less than 2ppm over the entire 2.7v to 5.5v supply range. ltc2415/ltc2415-1 16 sn2415 24151fs applicatio s i for atio wu u u frequency rejection selection ltc2415 (f o ) the ltc2415 internal oscillator provides better than 110db normal mode rejection at the line frequency and its harmon- ics for 50hz 2% or 60hz 2%. for 60hz rejection, f o should be connected to gnd while for 50hz rejection the f o pin should be connected to v cc . the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conver- sions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2415 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2415 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 7a. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2415 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside speci- fications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3a summarizes the duration of each state and the achievable output data rate as a function of f o . frequency rejection selection ltc2415-1 (f o ) the ltc2415-1 internal oscillator provides better than 87db normal mode rejection over the range of 49hz to 61.2hz as shown in figure 7b. for simultaneous 50hz/60hz rejection, f o should be connected to gnd. in order to achieve 87db normal mode rejection of 50hz 2% and 60hz 2%, two consecutive conversions must be averaged. by performing a continuous running average of the two most current results, both simultaneous rejection is achieved and a 2 increase in throughput is realized relative to the ltc2413 (see normal mode rejection, ouput rate and running averages sections of this data sheet). when a fundamental rejection frequency different from the range 49hz to 61.2hz is required or when the converter must be synchronized with an outside source, the ltc2415-1 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, t heo and t leo , are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2415-1 provides better than 110db normal mode rejection in a frequency range f eosc / 2560 4%. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 7a and figure 7c shows the normal mode rejection with running averages included. whenever an external clock is not present at the f o pin the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2415-1 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output ltc2415/ltc2415-1 17 sn2415 24151fs applicatio s i for atio wu u u table 3a. ltc2415 state duration state operating mode duration convert internal oscillator f o = low, (60hz rejection) 66.6ms, output data rate 15 readings/s f o = high, (50hz rejection) 80ms, output data rate 12.4 readings/s external oscillator f o = external oscillator with frequency 10278/f eosc s, output data rate f eosc /10278 readings/s f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low/high, (internal oscillator) as long as cs = low but not longer than 1.67ms (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms (32 sck cycles) frequency f eosc khz external serial clock with frequency f sck khz as long as cs = low but not longer than 32/f sck ms (32 sck cycles) input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 2415 f07a ?0 ?0 ?0 ?0 100 110 120 130 140 table 3b. ltc2415-1 state duration state operating mode duration convert internal oscillator f o = low 72.8ms, output data rate 14 readings/s simultaneous 50hz/60hz rejection external oscillator f o = external oscillator with frequency 10278/f eosc s, output data rate f eosc /10278 readings/s f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low (internal oscillator) as long as cs = low but not longer than 1.83ms (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms (32 sck cycles) frequency f eosc khz external serial clock with frequency f sck khz as long as cs = low but not longer than 32/f sck ms (32 sck cycles) figure 7c. ltc2415/ltc2415-1 normal mode rejection when using an external oscillator of frequency f eosc with running averages figure 7b. ltc2415-1 normal mode rejection when using an internal oscillator with running averages 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 2415 f07b ?0 ?0 100 100 120 130 140 differential input signal frequency deviation from notch frequency f eosc /2560(%) 12 8 404812 normal mode rejection (db) 2415 f07c ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 figure 7a. ltc2415/ltc2415-1 normal mode rejection when using an external oscillator of frequency f eosc without running averages state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3b summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2415/ltc2415-1 transmit the conversion results and receive the start of conversion command through a synchronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. ltc2415/ltc2415-1 18 sn2415 24151fs serial clock input/output (sck) the serial clock signal present on sck (pin 13) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2415/ltc2415-1 create their own se- rial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or float- ing at power-up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 12), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 11) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2415/ltc2415-1 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs=low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . tying a capacitor to cs will reduce the output rate and power dissipation by a factor proportional to the capacitors value, see figures 15 to 17. serial interface timing modes the ltc2415/ltc2415-1 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/exter- nal serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. table 4. ltc2415/ltc2415-1 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 8, 9 external sck, 2-wire i/o external sck sck figure 10 internal sck, single cycle conversion internal cs cs figures 11, 12 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 13 internal sck, autostart conversion internal c ext internal figure 14 applicatio s i for atio wu u u ltc2415/ltc2415-1 19 sn2415 24151fs applicatio s i for atio wu u u figure 8. external serial clock, single cycle operation eoc bit 31 sdo sck (external) cs test eoc sub lsb msb sig bit 0 lsb bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2415 f08 conversion = 50hz rejection (ltc2415) = external oscillator = 60hz rejection (ltc2415) = 50hz/60hz rejection (ltc2415-1) hi-z hi-z hi-z v cc test eoc test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2415/ ltc2415-1 3-wire spi interface the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device automatically enters the sleep state once the con- version is complete. while in the sleep state, if cs is high, the ltc2415/ltc2415-1 power consumption is reduced by an order of magnitude when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 32nd falling edge of sck, see figure 9. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for sys- tems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 10. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. ltc2415/ltc2415-1 20 sn2415 24151fs applicatio s i for atio wu u u figure 9. external serial clock, reduced data output length sdo sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2415 f09 msb sig bit 8 bit 27 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 3-wire spi interface 1 f 2.7v to 5.5v ltc2415/ ltc2415-1 = 50hz rejection (ltc2415) = external oscillator = 60hz rejection (ltc2415) = 50hz/60hz rejection (ltc2415-1) v cc since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion enters the sleep state. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 11. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s (ltc2415), 26 m s (ltc2415-1) if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven ltc2415/ltc2415-1 21 sn2415 24151fs applicatio s i for atio wu u u figure 10. external serial clock, cs = 0 operation (2-wire) figure 11. internal serial clock, single cycle operation eoc bit 31 sdo sck (external) cs msb sig bit 0 lsb 24 bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2415 f10 conversion v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire interface 1 f 2.7v to 5.5v ltc2415/ ltc2415-1 = 50hz rejection (ltc2415) = external oscillator = 60hz rejection (ltc2415) = 50hz/60hz rejection (ltc2415-1) v cc sdo sck (internal) cs msb sig bit 0 lsb 24 bit 5 test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2415 f11 ltc2415/ltc2415-1 24 sn2415 24151fs applicatio s i for atio wu u u figure 14. internal serial clock, autostart operation sdo hi-z hi-z sck (internal) cs v cc gnd 2415 f14 bit 0 sig bit 29 bit 30 sleep data output conversion conversion eoc bit 31 v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire interface 1 f 2.7v to 5.5v ltc2415/ ltc2415-1 c ext = 50hz rejection (ltc2415) = external oscillator = 60hz rejection (ltc2415) = 50hz/60hz rejection (ltc2415-1) v cc internal serial clock, autostart conversion this timing mode is identical to the internal serial clock, 2-wire i/o described above with one additional feature. instead of grounding cs, an external timing capacitor is tied to cs. while the conversion is in progress, the cs pin is held high by an internal weak pull-up. once the conversion is complete, the device enters the low power sleep state and an internal 25na current source begins discharging the capacitor tied to cs, see figure 14. the time the converter spends in the sleep state is determined by the value of the external timing capacitor, see figures 15 and 16. once the voltage at cs falls below an internal threshold ( ? 1.4v), the device automatically begins outputting data. the data output cycle begins on the first rising edge of sck and ends on the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. after the 32nd rising edge, cs is pulled high and a new conversion is immediately started. this is useful in appli- cations requiring periodic monitoring and ultralow power. figure 17 shows the average supply current as a function of capacitance on cs. it should be noticed that the external capacitor discharge current is kept very small in order to decrease the con- verter power dissipation in the sleep state. in the autostart mode, the analog voltage on the cs pin cannot be ob- served without disturbing the converter operation using a regular oscilloscope probe. when using this configura- tion, it is important to minimize the external leakage current at the cs pin by using a low leakage external capacitor and properly cleaning the pcb surface. the internal serial clock mode is selected every time the voltage on the cs pin crosses an internal threshold volt- age. an internal weak pull-up at the sck pin is active while cs is discharging; therefore, the internal serial clock timing mode is automatically selected if sck is floating. it is important to ensure there are no external drivers pulling sck low while cs is discharging. ltc2415/ltc2415-1 25 sn2415 24151fs applicatio s i for atio wu u u figure 15. cs capacitance vs t sample figure 16. cs capacitance vs output rate figure 17. cs capacitance vs supply current capacitance on cs (pf) 1 5 6 7 1000 10000 2415 f15 4 3 10 100 100000 2 1 0 t sample (sec) v cc = 5v v cc = 3v capacitance on cs (pf) 0 sample rate (hz) 3 4 5 1000 100000 2415 f16 2 1 0 10 100 10000 6 7 8 v cc = 5v v cc = 3v capacitance on cs (pf) 1 0 supply current ( a rms ) 50 100 150 200 250 300 10 100 1000 10000 2415 f17 100000 v cc = 5v v cc = 3v 66.6ms and the conversion time of the ltc2413 is 146ms, while the ltc2415-1 is 73ms. in systems where the sdo pin is monitored for the end-of-conversion signal (sdo goes low once the conversion is complete) these two devices can be interchanged. in cases where sdo is not monitored, a wait state is inserted between conversions, the duration of this wait state must be greater than 66.6ms for the ltc2415, greater than 133ms for the ltc2410, greater than 146ms for the ltc2413 and greater than 73ms for the ltc2415-1. preserving the converter accuracy the ltc2415/ltc2415-1 are designed to reduce as much as possible conversion result sensitivity to device decoupling, pcb layout, antialiasing circuits, line fre- quency perturbations and so on. nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. digital signal levels the ltc2415/ltc2415-1 digital interface is easy to use. its digital inputs (f o , cs and sck in external sck mode of operation) accept standard ttl/cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 m s. however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during conversion. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , cs and sck in external sck mode of operation) is within this range, the ltc2415/ltc2415-1 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. during the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the ltc2415/ timing compatibility with the ltc2410/ltc2413 all timing modes described above are identical with re- spect to the ltc2410/ltc2413 and ltc2415/ltc2415-1, with one exception. the conversion time of the ltc2410 is 133ms while the conversion time of the ltc2415 is ltc2415/ltc2415-1 26 sn2415 24151fs applicatio s i for atio wu u u ltc2415-1 pins may severely disturb the analog to digital conversion process. undershoot and overshoot can oc- cur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2415/ltc2415-1. for reference, on a regular fr-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared con- trol lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2415/ltc2415-1 pins will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the ltc2415/ltc2415-1 pins will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2415/ltc2415-1 are used with an external conversion clock. this clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this fre- quency. a normal mode signal of this frequency at the converter reference terminals may result into dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals may result into a dc offset error. such perturbations may occur due to asymmetric capaci- tive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference sig- nals. when the f o signal is parallel terminated near the converter, substantial ac current is flowing in the loop formed by the f o connection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. driving the input and reference the input and reference pins of the ltc2415/ltc2415-1 converters are directly connected to a network of sampling capacitors. depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. a simplified equivalent circuit is shown in figure 18. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 18), a first order passive network with a time constant t = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant t . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst- case circumstances, the errors may add. when using the internal oscillator (f o = low or high), the ltc2415s front-end switched-capacitor network is clocked at 76800hz corresponding to a 13 m s sampling period and the ltc2415-1s front end is clocked at 69900hz corre- sponding to 14.2 m s. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that t 13 m s/14 = 920ns (ltc2415) and t <14.2 m s/ 14 = 1.01 m s (ltc2415-1).. when an external oscillator of frequency f eosc is used, the sampling period is 2/f eosc and, for a settling error of less than 1ppm, t 0.14/f eosc . input current if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. an ltc2415/ltc2415-1 27 sn2415 24151fs applicatio s i for atio wu u u figure 18. ltc2415/ltc2415-1 equivalent analog input circuit figure 19. an rc network at in + and in C figure 21. Cfs error vs r source at in + or in C (small c in ) figure 20. +fs error vs r source at in + or in C (small c in ) iin vv v r iin vv v r i ref vv v r v vr i ref vv v r v vr where avg in incm refcm eq avg in incm refcm eq avg ref incm refcm eq in ref eq avg ref incm refcm eq in ref eq + - + - () = +- () = -+ - () = - + - () = - - + + 05 05 15 05 15 05 2 2 . . . . . . :: . . ./ . v ref ref v ref ref vinin v in in r m internal oscillator hz notch f low r m internal oscillator hz notch f high r f external oscillator r ref refcm in incm eq o eq o eq eosc eq =- = + ? ? ? ? =- = - ? ? ? ? == () == () = () = +- +- +- +- 2 2 361 60 432 50 0 555 10 397 12 w w ltc2415 ltc2415 m m internal oscillator hz hz notch f low o w 50 60 / = () ltc2415 -1 c in 2415 f19 v incm + 0.5v in r source in + ltc2415/ ltc2415-1 c par @ 20pf c in v incm ?0.5v in r source in c par @ 20pf r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2415 f20 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = 5v in = 2.5v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2415 f21 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf v ref + v in + v cc r sw (typ) 20k i leak i leak v cc i leak i leak v cc r sw (typ) 20k c eq 18pf (typ) r sw (typ) 20k i leak i in + v in i in i ref + i ref 2415 f18 i leak v cc i leak i leak switching frequency f sw = 76800hz internal oscillator (ltc2415) (f o = low or high) f sw = 69900hz internal oscillator (ltc2415-1) (f o = low) f sw = 0.5 ?f eosc external oscillator v ref r sw (typ) 20k incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the inl performance of the converter. figure 18 shows the mathematical expressions for the average bias currents flowing through the in + and in C pins as a result of the sampling charge transfers when integrated over a sub- stantial time period (longer than 64 internal clock cycles). the effect of this input dynamic current can be analyzed using the test circuit of figure 19. the c par capacitor includes the ltc2415/ltc2415-1 pin capacitance (5pf typical) plus the capacitance of the test fixture used to obtain the results shown in figures 20 and 21. a careful implementation can bring the total input capacitance (c in + c par ) closer to 5pf thus achieving better performance than the one predicted by figures 20 and 21. for simplic- ity, two distinct situations can be considered. ltc2415/ltc2415-1 28 sn2415 24151fs applicatio s i for atio wu u u for relatively small values of input capacitance (c in < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c in will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. nevertheless, when small values of c in are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the ltc2415/ltc2415-1 can maintain their exceptional accu- racy while operating with relative large values of source resistance as shown in figures 20 and 21. these mea- sured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. for small c in values, the settling on in + and in C occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. larger values of input capacitors (c in > 0.01 m f) may be required in certain configurations for antialiasing or gen- eral input signal filtering. such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. when f o = low (internal oscillator and 60hz notch), the typical differential input resistance is 1.8m w (ltc2415), 1.97m w (ltc2415-1) which will generate a gain error of approximately 0.28ppm for each ohm of source resis- tance driving in + or in C . for the ltc2415, when f o = high (internal oscillator and 50hz notch), the typical differential input resistance is 2.16m w which will generate a gain error of approximately 0.23ppm for each ohm of source resistance driving in + or in C . when f o is driven by an external oscillator with a frequency f eosc (external conver- sion clock operation), the typical differential input resis- tance is 0.28 ? 10 12 /f eosc w and each ohm of source resistance driving in + or in C will result in 1.78 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two input pins is additive with respect to this gain error. the typical +fs and Cfs errors as a function of the sum of the source resistance seen by in + and in C for large values of c in are shown in figures 22 and 23. in addition to this gain error, an offset error term may also appear. the offset error is proportional to the mismatch between the source impedance driving the two input pins in + and in C and with the difference between the input and reference common mode voltages. while the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the inl performance, indirect distortion may result from the modu- lation of the offset error by the common mode component of the input signal. thus, when using large c in capacitor values, it is advisable to carefully match the source imped- ance seen by the in + and in C pins. when f o = low (internal oscillator and 60hz notch), every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.28ppm. when f o = high (internal oscillator and 50hz notch), every 1 w mismatch in source impedance trans- forms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. when f o is driven by an external oscillator with a frequency f eosc , every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.78 ? 10 C6 ? f eosc ppm. figure 24 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the in + and in C pins when large c in values are used. if possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. this configuration eliminates the offset error caused by mismatched source impedances. the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are ltc2415/ltc2415-1 29 sn2415 24151fs applicatio s i for atio wu u u figure 22. +fs error vs r source at in + or in C (large c in ) figure 23. Cfs error vs r source at in + or in C (large c in ) figure 24. offset error vs common mode voltage (v incm = in + = in C ) and input source resistance imbalance ( d r in = r sourcein + C r sourcein C) for large c in values (c in 3 1 m f) r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2415 f22 300 240 180 120 60 0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2415 f23 0 ?0 120 180 240 300 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f v incm (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 offset error (ppm of v ref ) 2415 f24 120 100 80 60 40 20 0 ?0 ?0 ?0 ?0 100 120 f o = gnd t a = 25 c r sourcein ?= 500 c in = 10 f v cc = 5v ref + = 5v ref = gnd in + = in = v incm a: ? r in = +400 b: ? r in = +200 c: ? r in = +100 d: ? r in = 0 e: ? r in = 100 f: ? r in = 200 g: ? r in = 400 a b c d e f g used for the external source impedance seen by in + and in C , the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respec- tive values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na ( 10na max), results in a small offset shift. a 100 w source resistance will create a 0.1 m v typical and 1 m v maximum offset voltage. ltc2415/ltc2415-1 30 sn2415 24151fs applicatio s i for atio wu u u figure 25. +fs error vs r source at ref + or ref C (small c in ) figure 26. Cfs error vs r source at ref + or ref C (small c in ) figure 27. +fs error vs r source at ref + and ref C (large c ref ) figure 28. Cfs error vs r source at ref + and ref C (large c ref ) r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2415 f25 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = 5v in = 2.5v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2415 f26 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2415 f27 0 ?0 180 270 360 450 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2415 f28 450 360 270 180 90 0 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f reference current in a similar fashion, the ltc2415/ltc2415-1 sample the differential reference pins ref + and ref C transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in the same two distinct situa- tions. for relatively small values of the external reference capaci- tors (c ref < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. larger values of reference capacitors (c ref > 0.01 m f) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi con- stant reference differential impedance. for the ltc2415, when f o = low (internal oscillator and 60hz notch), the typical differential reference resistance is 1.3m w which will generate a gain error of approximately 0.38ppm for each ohm of source resistance driving ref + or ref C . when f o = high (internal oscillator and 50hz notch), the typical differential reference resistance is 1.56m w which will generate a gain error of approximately 0.32ppm for each ohm of source resistance driving ref + or ref C . for the ltc2415-1, the typical differential reference resis- ltc2415/ltc2415-1 31 sn2415 24151fs applicatio s i for atio wu u u figure 29. inl vs differential input voltage (v in = in + C in C ) and reference source resistance (r source at ref + and ref C for large c ref values (c ref 3 1 m f) v indif /v refdif ?.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 inl (ppm of v ref ) 15 12 9 6 3 0 ? ? ? ?2 ?5 v cc = 5v ref+ = 5v ref?= gnd v incm = 0.5 ?(in + + in ) = 2.5v f o = gnd c ref = 10 f t a = 25 c r source = 1000 r source = 500 r source = 100 2415 f29 tance is 1.43m w . when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differential reference resis- tance is 0.20 ? 10 12 /f eosc w and each ohm of source resistance driving ref + or ref C will result in 2.47 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two reference pins is additive with respect to this gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the ref + and ref C pins and external capacitance c ref connected to these pins are shown in figures 25, 26, 27 and 28. in addition to this gain error, the converter inl perfor- mance is degraded by the reference source impedance. when f o = low (internal oscillator and 60hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.34ppm additional inl error. for the ltc2415, when f o = high (internal oscillator and 50hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.1ppm additional inl error; and for the ltc2415-1 operating with simultaneous 50hz/60hz re- jection, every 100 w of source resistance leads to an additional 1.22ppm of additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 w of source resistance driving ref + or ref C translates into about 8.73 ? 10 C6 ? f eosc ppm additional inl error. figure 26 shows the typical inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the effect of the source resistance on the two reference pins is additive with respect to this inl error. in general, matching of source impedance for the ref + and ref C pins does not help the gain or the inl error. the user is thus advised to minimize the combined source impedance driving the ref + and ref C pins rather than to try to match it. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by ref + and ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be sufficient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a small gain error. a 100 w source resistance will create a 0.05 m v typical and 0.5 m v maxi- mum full-scale error. ltc2415/ltc2415-1 32 sn2415 24151fs applicatio s i for atio wu u u frequency at v in (hz) 1 120 rejection (db) 100 ?0 ?0 ?0 ?0 0 50 100 150 200 2415 f30 250 v cc = 5v v ref = 5v v in = 2.5v f o = 0 input frequency 0 ?0 ?0 0 2415 f31 ?0 ?00 f s /2 f s ?20 ?40 ?0 rejection (db) input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 2415 f32 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 2415 f33 ?0 ?0 100 100 120 130 140 input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2415 f34 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data figure 34. input normal mode rejection vs input frequency with input perturbation of 100% of full scale figure 30. rejection vs frequency at v in figure 31. rejection vs frequency at v in figure 32. rejection vs frequency at v in figure 33. normal mode rejection when using an internal oscillator normal mode rejection, output rate and running averages the ltc2415/ltc2415-1 both contain an identical sinc 4 digital filter (see figures 30 and 31) which offers excellent line frequency noise rejection. for the ltc2415, a notch frequency of either 50hz or 60hz (see figure 32) is user selectable by tying pin f o high or low, respectively. on the other hand, the ltc2415-1 offers simultaneous rejection of 50hz and 60hz by tying f o low. this sets the notch frequency to approximately 55hz (see figure 32). at a notch frequency of 55hz, the ltc2415-1 rejects 50hz 2% and 60hz 2% better than 72db. in order to achieve better than 87db rejection of both 50hz and 60hz 2%, a running average can be performed. by averaging two consecutive adc readings, a sinc 1 notch is combined with the sinc 4 digital filter yielding the frequency response shown in figures 33 and 34. in order to preserve the 2 output rate, adjacent results are averaged with the follow- ing algorithm: result 1 = average (sample 0, sample 1) result 2 = average (sample 1, sample 2) result 3 = average (sample 2, sample 3) result n = average (sample n-1, sample n) ltc2415/ltc2415-1 33 sn2415 24151fs applicatio s i for atio wu u u figure 36. connecting the ltc2415/ltc2415-1 to a 68hc11 mcu using the spi serial interface 2415 f35 ref + ref in + in 1, 7, 8, 9, 10, 15, 16 2 a0 a1 ltc2415/ ltc2415-1 v cc gnd 13 3 6 12 47 f 14 1 5 10 16 5v 15 11 2 to other devices 4 9 8 5v + 74hc4052 3 4 5 6 figure 35. use a differential multiplexer to expand channel capability ltc2415/ ltc2415-1 sck sdo cs 13 12 11 sck (pd4) miso (pd2) ss (pd5) 68hc11 2415 f36 sample driver for ltc2415/ltc2415-1 spi interface figure 35 shows the use of an ltc2415/ltc2415-1 with a differential multiplexer. this is an inexpensive multi- plexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. although the bridge output may be within the input range of the a/d and multiplexer in normal opera- tion, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or adc. the use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. the ltc2415/ltc2415-1 have a very simple serial inter- face that makes interfacing to microprocessors and microcontrollers very easy. the listing in figure 38 is a simple assembler routine for the 68hc11 microcontroller. it uses port d, configuring it for spi data transfer between the controller and the ltc2415/ltc2415-1 . figure 36 shows the simple 3-wire spi connection. the code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. this is followed by initializing port ds spi configuration. the program then enters the main sequence. it activates the ltc2415/ltc2415-1 serial interface by setting the ss output low, sending a logic low to cs. it next waits in a loop for a logic low on the data line, signifying end-of-conver- sion. after the loop is satisfied, four spi transfers are completed, retrieving the conversion. the main sequence ends by setting ss high. this places the ltc2415/ ltc2415-1 serial interface in a high impedance state and initiates another conversion. the performance of the ltc2415/ltc2415-1 can be verified using the demonstration board dc291a, see figure 40 for the schematic. this circuit uses the computers serial port to generate power and the spi digital signals necessary for starting a conversion and reading the result. it includes a labview application software program (see figure 39) which graphically cap- tures the conversion results. it can be used to determine noise performance, stability and with an external source, linearity. as exemplified in the schematic, the ltc2415/ ltc2415-1 are extremely easy to use. this demonstra- tion board and associated software is available by con- tacting linear technology. ltc2415/ltc2415-1 34 sn2415 24151fs applicatio s i for atio wu u u correlated double sampling with the ltc2415/ltc2415-1 figure 37 shows the ltc2415/ltc2415-1 in a correlated double sampling circuit that achieves a noise floor of under 100nv. in this scheme, the polarity of the bridge is alternated every other sample and the result is the average of a pair of samples of opposite sign. this technique has the benefit of canceling any fixed dc error components in the bridge, amplifiers and the converter, as these will alternate in polarity relative to the signal. offset voltages and currents, thermocouple voltages at junctions of dis- similar metals and the lower frequency components of 1/f noise are virtually eliminated. the ltc2415/ltc2415-1 have the virtue of being able to digitize an input voltage that is outside the range defined by the reference, thereby providing a simple means to implement a ratiometric example of correlated double sampling. this circuit uses a bipolar amplifier (lt1219u1 and u2) that has neither the lowest noise nor the highest gain. it does, however, have an output stage that can effectively suppress the conversion spikes from the ltc2415/ ltc2415-1. the lt1219 is a c-load tm stable amplifier that, by design, needs at least 0.1 m f output capacitance to remain stable. the 0.1 m f ceramic capacitors at the out- puts (c1 and c2) should be placed and routed to minimize lead inductance or their effectiveness in preventing enve- lope detection in the input stage will be reduced. alterna- tively, several smaller capacitors could be placed so that lead inductance is further reduced. this is a consideration because the frequency content of the conversion spikes extends to 50mhz or more. the output impedance of most op amps increases dramatically with frequency but the effective output impedance of the lt1219 remains low, determined by the esr and inductance of the capaci- tors above 10mhz. the conversion spikes that remain at the output of other bipolar amplifiers pass through the feedback network and often overdrive the input of the amplifier, producing envelope detection. rfi may also be present on the signal lines from the bridge; c3 and c4 provide rfi suppression at the signal input, as well as suppressing transient voltages during bridge commuta- tion. the wideband noise density of the lt1219 is 33nv ? hz, seemingly much noisier than the lowest noise amplifiers. however, in the region just below the 1/f corner that is not well suppressed by the correlated double sampling, the average noise density is similar to the noise density of many low noise amplifiers. if the amplifier is rolled off below about 1500hz, the total noise bandwidth is deter- mined by the converters sinc 4 filter at about 12hz. the use of correlated double sampling involves averaging even numbers of samples; hence, in this situation, two samples would be averaged to give an input-referred noise level of about 100nv rms . level shift transistors q4 and q5 are included to allow excitation voltages up to the maximum recommended for the bridge. in the case shown, if a 10v supply is used, the excitation voltage to the bridge is 8.5v and the outputs of the bridge are above the supply rail of the adc. u1 and u2 are also used to produce a level shift to bring the outputs within the input range of the converter. this instrumenta- tion amplifier topology does not require well-matched resistors in order to produce good cmrr. however, the use of r2 requires that r3 and r6 match well, as the common mode gain is approximately C12db. if the bridge is composed of four equal 350 w resistors, the differential component associated with mismatch of r3 and r6 is nearly constant with either polarity of excitation and, as with offset, its contribution is canceled. c-load is a trademark of linear technology corporation. ltc2415/ltc2415-1 35 sn2415 24151fs applicatio s i for atio wu u u + + u1 lt1219 u2 lt1219 5k 5k c1 0.1 f c2 0.1 f r3 10k r6 10k c4 2.2nf c3 2.2nf r4 499 r5 499 10v 10v 1000pf 1000pf 1k 1k r2 27k 10v difference amp 33 100 r1 61.9 0.1% q1 22 22 22 22 74hc04 350 4 5v 5v 2.7k 2.7k 100 100 1.5k 1.5k eliminate for 5v operation (connect 2.7k resistors to 100 resistors) q4 q5 q2 q3 5v pol q1: q2, q3: q4, q5: siliconix si9802dy (800) 554-5565 mmbd2907 mmbd3904 0.1 f 0.1 f 3 2 4 5 6 7 shdn 2 3 4 5 6 7 shdn 5 6 3 4 30pf 2415 f37 30pf in + in ref + ref gnd ltc2415/ ltc2415-1 figure 37. correlated double sampling resolves 100nv ltc2415/ltc2415-1 36 sn2415 24151fs typical applicatio s u ************************************************************ * this example program transfers the ltc2415/ltc2415-1 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ************************************************************ *68hc11 register definition portd equ $1008 port d data register * " C , C , ss* ,csk ;mosi,miso,txd ,rxd" ddrd equ $1009 port d data direction register spsr equ $1028 spi control register * "spie,spe ,dwom,mstr;spol,cpha,spr1,spr0" spsr equ $1029 spi status register * "spif,wcol, C ,modf; C , C , C , C " spdr equ $102a spi data register; read-buffer; write-shifter * * ram variables to hold the ltc2415/ltc2415-1s 32 conversion result * din1 equ $00 this memory location holds the ltc2415/ltc2415-1s bits 31 - 24 din2 equ $01 this memory location holds the ltc2415/ltc2415-1s bits 23 - 16 din3 equ $02 this memory location holds the ltc2415/ltc2415-1s bits 15 - 08 din4 equ $03 this memory location holds the ltc2415/ltc2415-1s bits 07 - 00 * ********************** * start getdata routine * ********************** * org $c000 program start location init1 lds #$cfff top of c page ram, beginning location of stack ldaa #$2f C,C,1,0;1,1,1,1 * C, C, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit 5 is set ldaa #$38 C,C,1,1;1,0,0,0 staa ddrd ss*, sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs *ddrds bit 5 is a 1 so that port ds ss* pin is a general output ldaa #$50 staa spcr the spi is configured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 * (this assumes an e-clock frequency of 4mhz. for higher e- * clock frequencies, change the above value of $50 to a value * that ensures the sck frequency is 2mhz or less.) getdata pshx pshy psha ldx #$0 the x register is used as a pointer to the memory locations * that hold the conversion data ldy #$1000 bclr portd, y %00100000 this sets the ss* output bit to a logic * low, selecting the ltc2415/ltc2415-1 * ltc2415/ltc2415-1 37 sn2415 24151fs typical applicatio s u ******************************************** * the next short loop waits for the * * ltc2415/ltc2415-1s conversion to finish before * * starting the spi data transfer * ******************************************** * convend ldaa portd retrieve the contents of port d anda #%00000100 look at bit 2 * bit 2 = hi; the ltc2415/ltc2415-1s conversion is not * complete * bit 2 = lo; the ltc2415/ltc2415-1s conversion is complete bne convend branch to the loops beginning while bit 2 remains high * * ******************** * the spi data transfer * ******************** * trflp1 ldaa #$0 load accumulator a with a null byte for spi transfer staa spdr this writes the byte in the spi data register and starts * the transfer wait1 ldaa spsr this loop waits for the spi to complete a serial transfer/exchange by reading the spi status register bpl wait1 the spif (spi transfer complete flag) bit is the spsrs msb * and is set to one at the end of an spi transfer. the branch * will occur while spif is a zero. ldaa spdr load accumulator a with the current byte of ltc2415/ltc2415-1 data that was just received staa 0,x transfer the ltc2415/ltc2415-1s data to memory inx increment the pointer cpx #din4+1 has the last byte been transferred/exchanged? bne trflp1 if the last byte has not been reached, then proceed to the * next byte for transfer/exchange bset portd,y %00100000 this sets the ss* output bit to a logic high, * de-selecting the ltc2415/ltc2415-1 pula restore the a register puly restore the y register pulx restore the x register rts figure 38. this is an example of 68hc11 code that captures the ltc2415/ltc2415-1 conversion results over the spi serial interface shown in figure 40 ltc2415/ltc2415-1 38 sn2415 24151fs pcb layout a d fil uw silkscreen top top layer differential input 24-bit adc with 2 output rate demo circuit dc382 www.linear-tech.com ltc confidential for customer use only ltc2415cgn figure 39. display graphic typical applicatio s u ltc2415/ltc2415-1 39 sn2415 24151fs package descriptio u gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.009 (0.229) ref gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. pcb layout a d fil uw bottom layer ltc2415/ltc2415-1 40 sn2415 24151fs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 lt/tp 0202 2k ? printed in usa related parts part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max initial accuracy lt1025 micropower thermocouple cold junction compensator 80 m a supply current, 0.5 c initial accuracy ltc1043 dual precision instrumentation switched capacitor precise charge, balanced switching, low power building block ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/ c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/ c max drift, ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ds adcs in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2414/ltc2418 4-/8-channel, 24-bit, no latency ds adcs with differential inputs 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2410 24-bit, no latency ds adc with differential inputs 800nv rms noise, pin compatible with ltc2415 ltc2411 24-bit, no latency ds adc with differential inputs in msop 1.45 m v rms noise, 4ppm inl ltc2413 24-bit, no latency ds adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2420 20-bit, no latency ds adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 figure 40. 24-bit a/d demo board schematic jp4 jumper 2 3 1 1 p1 db9 6 9 2 7 3 8 4 5 + 2415 f40 r1 10 w j1 v ext d1 bav74lt1 c4 100 f 16v v out v in gnd u2 lt1236acn8-5 u3e 74hc14 62 11 10 14 3 13 4 12 5 16 6 15 10 9 8 7 1 11 2 3 21 1 1 4 u3f 74hc14 13 12 u3b 74hc14 3 4 u3a 74hc14 1 2 u3c 74hc14 6 5 u3d 74hc14 8 3 2 1 9 + c3 10 f 35v v out v in gnd u1 lt1460acn8-2.5 62 4 + c1 10 f 35v + c2 22 f 25v c6 0.1 f + c5 10 f 35v v cc v cc v cc j2 gnd j3 v cc 1 1 j5 gnd 1 j7 ref banana jack 1 j6 ref + banana jack 1 j4 v ext banana jack 1 j8 v in + banana jack 1 j9 v in banana jack 1 j10 gnd banana jack r3 51k r4 51k r6 3k q1 mmbt3904lt1 r5 49.9 r7 22k r8 51k ref + f o ref sck v in + sdo v in gnd gnd gnd cs v cc gnd gnd gnd gnd jp3 jumper 2 3 1 c7 0.1 f bypass cap for u3 notes: install jumber jp1 at pin 1 and pin 2 install jumber jp2 at pin 1 and pin 2 install jumber jp3 at pin 1 and pin 2 v cc jp5 jumper 1 2 jp1 jumper 2 3 1 jp2 jumper 2 1 r2 3 u4 ltc2415/ ltc2415-1 typical applicatio u |
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